I. Field
The present disclosure relates generally to electronics, and more specifically to a decimator.
II. Background
A decimator is a circuit block that receives an input signal at an input sample rate and provides an output signal at an output sample rate that is a fraction of the input sample rate. The decimation process may result in undesired signal components at harmonics of the output sample rate to fall within a desired signal bandwidth. These undesired signal components would then act as noise that may degrade performance. An anti-alias filter may be placed prior to the decimator and may be used to attenuate the undesired signal components that can fall within the desired signal bandwidth. The anti-alias filter may be relatively complex depending on the input and output sample rates and the desired amount of attenuation of the undesired signal components. It is desirable to perform decimation in a manner that can reduce hardware complexity.